Hardware reconfiguration
of RISC-V GD32VF
in noForth r(cv)
Data needed for the hardware initialization
(Clock frequency, UART, Baudrate and the S? button)
is stored in 5 cells at address CFG.
What to do if you want to change something:
- See the options below and choose the desired one.
- Copy the code in the colored box.
- Send the code to noForth (store and initialize).
- Test the new situation.
- No problems? Then make it permanent with FREEZE
Clock, UART and Baudrate - cells 0-3
RCU_CFG0 = Clock Configuration Register-
Clock 104 MHz - Baudrate 115k2 - UART 0
hx AD,C402 0 cells cfg + ! \ RCU_CFG0 dm 104,000,000 1 cells cfg + ! \ Clock frequency 0 2 cells cfg + ! \ Select UART dm 115,200 3 cells cfg + ! \ Baudrate cfg config \ Initialize -
Clock 72 MHz - Baudrate 115k2 - UART 0
hx 1D,8402 0 cells cfg + ! \ RCU_CFG0 dm 72,000,000 1 cells cfg + ! \ Clock frequency 0 2 cells cfg + ! \ Select UART dm 115,200 3 cells cfg + ! \ Baudrate cfg config \ Initialize -
Clock 8 MHz - Baudrate 38k4 - UART 0
0 0 cells cfg + ! \ RCU_CFG0 dm 8,000,000 1 cells cfg + ! \ Clock frequency 0 2 cells cfg + ! \ Select UART dm 38,400 3 cells cfg + ! \ Baudrate cfg config \ InitializeS? button - cells 4-5
-
For Sipeed Longan Nano board - S? on PA.8
hx 4001,0800 4 cells cfg + ! \ Port address dm 8 5 cells cfg + ! \ I/O-bit cfg config \ Initialize -
For SEEED GD32VF dev board - S? on PA.0
hx 4001,0800 4 cells cfg + ! \ Port address 0 5 cells cfg + ! \ I/O-bit cfg config \ Initialize -
For SEEED GD32VF dev board - S? on PC.13
hx 4001,1000 4 cells cfg + ! \ Port address dm 13 5 cells cfg + ! \ I/O-bit cfg config \ Initialize*